Many data communication systems use error correction encoders and decoders to detect and correct errors in data. Storage systems are frequently modeled as a communication system with a delay, where data is transmitted during a write operation and data is received at a read operation. In a storage system, random errors can be corrected up to a rate of about 1×10−4 with an acceptable overhead. To protect against an error rate of about 1×10−4, an error correction encoder may generate encoded bits having about 10% more bits than its input bits.
Phase change memory (PCM) is a class of non-volatile semiconductor memory. PCM devices have many advantages over traditional non-volatile flash memory. However, PCM devices may generate a large number of errors that are induced by writing cycle degradation. For example, a PCM device may generate errors at a rate of 1×10−2 or greater if cycled to millions or tens of millions of cycles.
At the limits of endurance, the error rate in non-volatile memory devices is dominated by writing cycle degradation, not by random errors. Errors that are dominated by degradation include stuck-at faults and unstable bits. Each of these two types of errors have different statistics than the random errors that are commonly assumed in data communication systems and corresponding error correcting approaches.